Cycle Accurate Simulation Model Generation for SoC Prototyping
Résumé
We present new results concerning the integration of high level designed ips into a complete System on Chip. We first introduce a new compu- tation model that can be used for cycle accurate simulation of register transfer level synthesized hardware. Then we provide simulation of a SoC integrating a data-flow ip synthesized with MMAlpha and the So- cLib cycle accurate simulation environment. This integration also vali- dates an efficient generic interface mechanism for data-flow ips.
Domaines
Modélisation et simulation| Origine | Fichiers produits par l'(les) auteur(s) |
|---|
Loading...