Efficient on-chip communications for data-flow IPs - Archive ouverte HAL Accéder directement au contenu
Communication Dans Un Congrès Année : 2004

Efficient on-chip communications for data-flow IPs

Résumé

We explain a systematic way of interfacing data-flow hardware accelerators (IP) for their integration in a system on chip. We abstract the communication behaviour of the data flow IP so as to provide basis for an interface generator. We also explain which parameter this interface generator has to take into account. We validate our interface mechanism by a cycle accurate bit accurate simulation of a SoC integrating a data-flow ip.
Fichier principal
Vignette du fichier
ASAP04.pdf (135.75 Ko) Télécharger le fichier
Origine : Fichiers produits par l'(les) auteur(s)
Loading...

Dates et versions

hal-00399632 , version 1 (27-06-2009)

Identifiants

Citer

Antoine Fraboulet, Tanguy Risset. Efficient on-chip communications for data-flow IPs. Application-Specific Systems, Architectures and Processors, 2004, Galveston, Texas, United States. pp.293- 303, ⟨10.1109/ASAP.2004.1342479⟩. ⟨hal-00399632⟩
136 Consultations
230 Téléchargements

Altmetric

Partager

Gmail Facebook X LinkedIn More