Plasma etching challenges of new materials involved in gate stack patterning for sub 45nm technological node
Résumé
In ULSI technology, plasma etch processes at the front end level are becoming increasingly complex. First of all, dimensions are continuously shrinking since we are now reaching gate dimensions of about 40 nm for the 65 nm node and below 30 nm for the 45 nm nodes. Complexity is also coming from the introduction of very complex gate stacks. The simple Poly Si/SiO 2 gate stack will be replaced in the future by more complex structures such as Poly Si/Metal/ High k dielectrics. The introduction of these new materials bring many new issues that need to be adressed in order to make gate structures with well controlled dimensions, good profile control and high selectivities with respect to the silicon wafer. In this paper, we report the etching of Poly Si/metal/HfO 2 gate stacks and concentrate more specifically on the TiN and TaN metals. The following points will be addressed:
- impact of the metal layer on charging effects and consequences on profile control. In particular it is shown that the notching effect of the soft landing step induced by the presence of the gate dielectric at the end of polysilicon etch step is suppressed when the plasma lands on a metal, leading to strong foot formation at the bottom of the polysilicon layer.
- influence of the metal layer on the sequence of steps of the process (stop on metal layer after poly etch or etch the Poly/metal stack in one step). It is shown that a notch can be easily formed at the poly/metal interface when the Poly/metal stack is not etched in one step.
- choice of chemistry to etch the metal layer and impact on the polysilicon profile control. We will compare typical chemistries such as Cl2/HBr and CF4 chemistries on the final profile control of the gate.
- impact of metal etching chemistry on the passivation layer formed on the polysilicon sidewalls.
