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Journal Articles IEEE Design & Test Year : 2008

Multisynchronous and Fully Asynchronous NoCs for GALS Architectures

Abstract

Networks on chips constitute a new design paradigm for communication infrastructures in large multiprocessor SoCs. NoCs can use the GALS technique to address the difficulty of distributing a synchronous clock signal on the entire chip area. This article describes two approaches to implementing a distributed NoC in a GALS environment.
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hal-00367212 , version 1 (10-03-2009)

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Abbas Sheibanyrad, Alain Greiner, Ivan Miro-Panades. Multisynchronous and Fully Asynchronous NoCs for GALS Architectures. IEEE Design & Test, 2008, 25 (6), pp.572-580. ⟨10.1109/MDT.2008.167⟩. ⟨hal-00367212⟩
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