Generic description and synthesis of LDPC decoder
Résumé
Through a rapid survey of the architec ture of Low-Density Parity-Check (LDPC) decoders, this paper proposes a general framework to describe and compare LDPC decoder architectures. A set of parameters makes it possible to classify the scheduling of iterative decoders, memory organization and type of check node processors and variable node processors. Using the proposed framework, an efficient generic architecture for non-fooding schedules is also given.
Domaines
Electronique| Origine | Fichiers produits par l'(les) auteur(s) |
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