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Communication Dans Un Congrès Année : 2008

A Secure Programmable Architecture with a Dedicated Tech-mapping Algorithm: Application to a Crypto-Processor

Résumé

With worldwide communications, information technology and confidentiality have become a major issue for exchanging and securing data. Nevertheless the ASIC high costs and the frequent updates in cryptographic standards used in security applications such as homeland security or banking have made the ciphering algorithms on an embedded FPGA (e-FPGA) co-processor a viable alternative. This paper presents a secure e-FPGA architecture dedicated to security applications, which is able to support asynchronous crypto-processor implementations in order to defeat side-channel attacks. The proposed architecture is natively robust against attacks such as differential power analysis (DPA) or clock based fault attacks. The article also presents a specific tech-mapping algorithm for implementing asynchronous dual rail functions on this e-FPGA. This algorithm respects the security constraints to be robust against DPA. Electrical simulations on a sensitive crypto-processor module validate the proposed approach.

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Dates et versions

hal-00346734 , version 1 (12-12-2008)

Identifiants

  • HAL Id : hal-00346734 , version 1

Citer

T. Beyrouthy, Laurent Fesquet, Alin Razafindraibe, S. Chaudhuri, S. Guilley, et al.. A Secure Programmable Architecture with a Dedicated Tech-mapping Algorithm: Application to a Crypto-Processor. 23rd International Conference on Design of Circuits and Integrated Systems (DCIS'08), Nov 2008, Grenoble, France. pp.session 3b3. ⟨hal-00346734⟩
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