Physical Design of FPGA Interconnect to Prevent Information Leakage - Archive ouverte HAL
Chapitre D'ouvrage Année : 2008

Physical Design of FPGA Interconnect to Prevent Information Leakage

Résumé

In this article we discuss dual/multi-rail routing techniques in an island style FPGA for robustness against side-channel attacks. We present a technique to achieve dual-rail routing balanced in both timing and power consumption with the traditional subset switchbox. Secondly, we propose two switchboxes (namely: Twist-on-Turn & Twist-Always) to route every dual/multi-rail signal in twisted pairs, which can deter electromagnetic attacks. These novel switchboxes can also be balanced in power consumption albeit with some added cost. We present a layout with pre-placed switches and pre-routed balanced wires and extraction statistics about the expected balance. As conclusion, we discuss various overheads associated with these techniques and possible improvements.

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Dates et versions

hal-00299487 , version 1 (17-07-2008)

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Citer

Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, et al.. Physical Design of FPGA Interconnect to Prevent Information Leakage. Woods, R.; Compton, K.; Bourganis, C.; Diniz, P.C. Reconfigurable Computing: Architecture, Tools, and Applications, 4943, Springer, pp.87-98, 2008, Lecture Notes in Computer Science, ⟨10.1007/978-3-540-78610-8_11⟩. ⟨hal-00299487⟩
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