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Communication Dans Un Congrès Année : 2008

New Directions in Interconnect Performance Optimization

Résumé

It is now admitted that interconnects represent a bottleneck for delay, power consumption and area on chips. To face these problems some works have been realized around performance optimizations. However results, presented in this paper, show that optimization techniques do not always face good criteria for interconnect performance optimizations. We therefore have developed a high-level estimation tool based on transistor-level characterizations, which provides users fast and precise results for time and power consumption estimation. Estimation results allowed us to determine a new interconnect consumption model and also enabled to find some new key issues that have to be pointed out for future performance optimizations.
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Dates et versions

hal-00294132 , version 1 (08-07-2008)

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Citer

Antoine Courtay, Johann Laurent, Nathalie Julien, Olivier Sentieys. New Directions in Interconnect Performance Optimization. 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2008. DTIS 2008., Mar 2008, Tozeur, Tunisia. pp.6, ⟨10.1109/DTIS.2008.4540228⟩. ⟨hal-00294132⟩
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