Low power implementation of decimation filter for multistandard receiver - Archive ouverte HAL Accéder directement au contenu
Communication Dans Un Congrès Année : 2008

Low power implementation of decimation filter for multistandard receiver

N. Khouja
  • Fonction : Auteur
K. Grati
  • Fonction : Auteur
A. Ghazel
  • Fonction : Auteur

Résumé

This work deals with low-power design of a decimation filter used in a wireless multi-standard receiver. We propose a solution that reduces the dynamic power consumption by reducing the filtering activity. This solution uses the clock-gating technique on parallel filters combined with appropriate clock distribution. We optimize the arithmetic operators to save area with the power consumption and increase the operating frequency. The new design saves about thirty percent of consumed power compared to a solution using only the clock-gating technique.

Domaines

Electronique
Fichier non déposé

Dates et versions

hal-00288655 , version 1 (17-06-2008)

Identifiants

  • HAL Id : hal-00288655 , version 1

Citer

N. Khouja, K. Grati, A. Ghazel, Bertrand Le Gal. Low power implementation of decimation filter for multistandard receiver. IEEE Design and Technology of Integrated Systems (DTIS'08), Mar 2008, Tozeur, Tunisia. pp.00. ⟨hal-00288655⟩
36 Consultations
0 Téléchargements

Partager

Gmail Facebook X LinkedIn More