Functional Verification of RTL Designs driven by Mutation Testing metrics - Archive ouverte HAL Accéder directement au contenu
Communication Dans Un Congrès Année : 2007

Functional Verification of RTL Designs driven by Mutation Testing metrics

Youssef Serrestou
  • Fonction : Auteur
  • PersonId : 846817

Résumé

The level of confidence in a VHDL description directly depends on the quality of its verification. This quality can be evaluated by mutation-based test, but the improvement of this quality requires tremendous efforts. In this paper, we propose a new approach that both qualifies and improves the functional verification process. First, we qualify test cases thanks to the mutation testing metrics: faults are injected in the Design Under Verification (DUV) (making DUV's mutants) to check the capacity of test cases to detect theses mutants. Then, a heuristic is used to automatically improve IPs validation data. Experimental results obtained on RTL descriptions from ITC'99 benchmark show how efficient is our approach.
Fichier non déposé

Dates et versions

hal-00254470 , version 1 (13-02-2008)

Identifiants

Citer

Youssef Serrestou, Vincent Beroulle, Chantal Robach. Functional Verification of RTL Designs driven by Mutation Testing metrics. 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, 2007. DSD 2007., Aug 2007, Lubeck, Germany. pp.222-227, ⟨10.1109/DSD.2007.4341472⟩. ⟨hal-00254470⟩

Collections

UGA LCIS
118 Consultations
0 Téléchargements

Altmetric

Partager

Gmail Facebook X LinkedIn More