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Communication Dans Un Congrès Année : 2006

How to Improve a set of design validation data by using mutation-based test

Youssef Serrestou
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Résumé

In current hardware design flow, functional verification is widely acknowledged as the crucial step. This paper presents a new contribution to reduce the cost of this step by automating it. We address here, one of the principal challenges of dynamic verification, by providing a new approach for automatic test generation. This approach combines mutation-based test techniques and genetic algorithms to produce stimuli for design under test. The feasibility of the proposed approach is assessed with a preliminary implementation, and some framework has been tested.
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Dates et versions

hal-00254378 , version 1 (13-02-2008)

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  • HAL Id : hal-00254378 , version 1

Citer

Youssef Serrestou, Chantal Robach, Vincent Beroulle. How to Improve a set of design validation data by using mutation-based test. 2006 IEEE Design and Diagnostics of Electronic Circuits and systems, Apr 2006, Prague, Czech Republic. pp.75-76. ⟨hal-00254378⟩

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