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Communication Dans Un Congrès Année : 2007

An on-pixel FPN reduction method for a high dynamic range CMOS imager

Résumé

A high dynamic range CMOS image sensor implementing a fixed pattern noise (FPN) reduction method is presented. The high dynamic range is reach through a logarithmic architecture pixel. An on-chip calibration method is implemented to reduce the FPN caused by process variations, weakness of this architecture. The basic principle is the calibration of each pixel against an in-pixel reference current in place of the diode photocurrent. Two pixel levels corresponding to the photocurrent and a known reference current become available for every pixel. Then a double sampling technique allows removing offsets due to threshold voltage variations. An innovation of this work consists in the implementation of the current calibration source totally inside the pixel, allowing a better precision of the FPN compensation and lower power consumption. This FPN reduction method is performed while keeping only four transistors per pixel. A 128×128 pixels test chip has been designed and fabricated in 0.35μm, 3.3V CMOS standard technology. Pixel measures 10×10.6μm2 with a fill factor of 33%. The dynamic range is up to l00dB with a frame rate up to 30 images per second and a measured FPN of 2.9%rms of the total dynamic range.

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Dates et versions

hal-00222814 , version 1 (29-01-2008)

Identifiants

  • HAL Id : hal-00222814 , version 1

Citer

Estelle Lauga-Larroze, G. Sicard, Marc Renaudin. An on-pixel FPN reduction method for a high dynamic range CMOS imager. 33rd European Solid-State Circuits Conference (ESSCIRC'07), Sep 2007, Munich, Germany. pp.332-335. ⟨hal-00222814⟩

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