The test cost of heterogeneous integrated circuits has significantly increased. So, the definition of relevant test methods and efficient test stimuli are becoming crucial research orientations for semiconductor manufacturers. In this paper, we propose to decrease the manufacturing test cost of AMS&RF System-on-Chips (SoC) by automatically qualifying and optimizing existing test set. We will present a Computed Aided Test tool PLASMA that uses faults injection and faults simulation technique to perform the test qualification and generation. This tool reduces both test time and test equipments cost using a high-level fault model. After discussing on the advantages of the choice of behavioral faults models, we present a method that allows us to decrease the overall simulation times. This method proposes to reduce the number of simulated fault-free models thanks to a normal estimation.