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Communication Dans Un Congrès Année : 2008

Design of Class-E Power VCO in 65nm CMOS Technology: Application to RF Transmitter Architecture

Résumé

This paper investigates the feasibility of designing a RF TX architecture based on a Power VCO, operating at 1.95 GHz for UMTS/WCDMA standard. The Power VCO uses 2.5 V supply voltage and is designed using 65nm CMOS technology from ST Microelectronics. The Power VCO is made up of an oscillating Power Amplifier (PA). In order to fulfil UMTS/W CDMA requirements, especially on output power with regards to efficiency to save battery life, the used PA is a two-stage Class E PA. The output 1 dB compression point (CP1) is 22 dBm and Power Added Efficiency (PAE) @CP1 is 55.1%. This PA is then included in a loop to realize oscillation condition. The Power VCO oscillates @ 1.95GHz, achieves an output power of 23.3dBm with 60.3% PAE
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Dates et versions

hal-00207360 , version 1 (17-01-2008)

Identifiants

  • HAL Id : hal-00207360 , version 1

Citer

Nathalie Deltimple, Yann Deval, Eric Kerherve, Didier Belot. Design of Class-E Power VCO in 65nm CMOS Technology: Application to RF Transmitter Architecture. 2008 IEEE International Symposium on Circuits and Systems (ISCAS2008), May 2008, Seattle, United States. pp. ⟨hal-00207360⟩
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