High robustness PNP-based structure for the ESD protection of high voltage I/Os in an advanced smart power technology
Résumé
A new device dedicated to the ESD protection of high voltage I/Os is presented. In addition to the use of specific design guidelines, the concept consists in coupling an open-base lateral PNP with a vertical avalanche diode within the same structure to obtain a non-snapback behavior together with very good RON capabilities (~1Ω). The protection of high voltage I/Os with a narrow ESD design window ranging from 80V to 100V can be implemented in a reduced surface of 151*140 μm2, which represents a state-of-the-art breakthrough.
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