The Networks on Chip (NoCs) paradigm has recently emerged as an alternative solution for large complex SoCs' communication. Despite having many attractive attributes, NoCs design has also lots of challenges. One of the challenges is testing network architectures (routers and communication channels) for manufacturing defects, especially, the test of asynchronous NoCs. To improve the testability of asynchronous NoCs, we have developed a scalable and configurable fully asynchronous Design-for-Test (DfT) architecture. In this architecture, each asynchronous network node is surrounded by an asynchronous test wrapper and the network communication channels are reused as a high throughput Test Access Mechanism (TAM). This paper presents the realization and implementation of this DfT architecture. The validation and experimental results are also presented.