The layout of Power Multichip Modules is one of the key points of a module design, especially for high power densities, where coupling are enlarged. This paper focuses on dynamic current imbalance between paralleled chips. It can be principally attributed to gate circuit dissymmetry, which modifies inductances and coupling, especially with the power circuit. This paper describes the analysis of an existing power module, and based on a modification of the gate circuit geometry in an optimization procedure, shows how to improve the power module, in term of dynamic current repartition.