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Communication Dans Un Congrès Année : 2007

A 10-Gb/s CMOS Fully Integrated ILO-based CDR

Résumé

A CDR circuit dedicated to satellite embedded data link is presented. This circuit combines an injection locked oscillator, with a phase alignment circuit, to achieve the clock recovery. The circuit was designed in a 130 nm CMOS process from STMicroelectronics. The working range is from 9.6 Gbit/s up to 10.2 Gbit/s, the power dissipation is 94 mW under 1.2 V power supply. The measured eye opening is 60 ps and 240 mV with a BER lower than 10-12.
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Dates et versions

hal-00182300 , version 1 (25-10-2007)

Identifiants

  • HAL Id : hal-00182300 , version 1

Citer

Olivier Mazouffre, Birama Goumballa, Michel Pignol, Claude Neveu, Yann Deval, et al.. A 10-Gb/s CMOS Fully Integrated ILO-based CDR. European Solid-State Circuits Conference, Sep 2007, Munich, Germany. pp.520-523. ⟨hal-00182300⟩
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