Applications in signal and image processing have to cope with hard constraints such as high reconfigurability, real-time performance and low power consumption. On one hand actual researches try to reduce algorithm calculation complexity using ad-hoc solution composed of conditional computations (transformation of the Full Search algorithm for Block Matching to a Three Step Search algorithm). These algorithms improvements lead to execution hazards to appear with conditional and unbounded loop usages. On the other hand other researches based on architectural implementations of these algorithms under real-time constraints tries to exploit operation parallelism, budgeting computations on the cadency/latency constraint. Optimized architectures are obtained for regular algorithm without execution hazard. These two ways are conflicting, so for two families of architectures are used for there implementation: the first one which is commonly used in general processors and uses interaction between control and data parts. It computes conditions and loop reiteration tests in the data path and send result using state register, to the controller which takes the loop termination or branch selection decision, this induces hazard penalties due to conditional result transfer. The second architectural solution consists in regular budget of computations; it manages condition computations and speculative executions directly in the data-path without sending information to the control unit, calculating all condition branches and iterations to the maximum specified bound. Therefore, in High-Level Synthesis for VLIW we need guidelines to select the best architecture for the targeted application. The final paper will present GAUT High-Level Synthesis design flow, and a simulator tool which allows analyzing and validating an architectural choice. It will also present execution results (number of cycles) for different applications mapped on the both architectures showing the interest of our study.