How to Implement an Asynchronous Test Wrapper for Network-on-Chip Nodes - Archive ouverte HAL
Communication Dans Un Congrès Année : 2007

How to Implement an Asynchronous Test Wrapper for Network-on-Chip Nodes

Résumé

The Network-on-Chip (NoC) paradigm is currently known as an alternative solution for the on chip communication in the next SoC generation, especially, asynchronous NoCs. One of the challenges for asynchronous NoC-based systems design is testing asynchronous network architectures for manufacturing defects. To improve the testability of asynchronous NoCs, we have developed a scalable and configurable asynchronous Design-for-Test (DfT) architecture. In this architecture, each asynchronous network node is surrounded by an asynchronous test wrapper and the network communication channels are reused as a high-speed Test Access Mechanism (TAM). This architecture is designed to test all network elements (routers, communication channels), but it can also be used to test computational resources. In this paper, we introduce how to realize and implement the test wrapper in Quasi Delay Insensitive (QDI) asynchronous logic style. The validation and experimental results are also presented.
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Dates et versions

hal-00166373 , version 1 (05-08-2007)

Identifiants

  • HAL Id : hal-00166373 , version 1

Citer

Xuan Tu Tran, Jean Durupt, François Bertrand, Vincent Beroulle, Chantal Robach. How to Implement an Asynchronous Test Wrapper for Network-on-Chip Nodes. The 12th IEEE European Test Symposium (ETS 2007), May 2007, Freiburg, Germany. pp.Tran07HTI. ⟨hal-00166373⟩
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