This work presents probabilistic methods for testability analysis at RTL and their use to evaluate the sensitivity of a digital circuit to Single Event Upsets (SEUs). A new probabilistic testability metric is proposed, in order to evaluate if the possible changes caused by SEUs are ignored or propagated by the dynamic behavior of the circuit. The new metric, event detectability, is defined based on the recently proposed event observability metric combined with the controllability. A methodology for error rate prediction based on the new metric is proposed. The testability analysis methods were implemented in a tool (ASCOPA) that takes as input a Verilog RTL description, solves the Chapman-Kolmogorov equations that describe the steady-state of the circuit, and outputs the computed values for the testability metrics. The proposed metric is used to obtain the relation between the static and the dynamic SEUs cross-section for ITC'99 benchmark circuits. It is shown that the error probability, for the b04 benchmark, can be 50% reduced using only 1/3 of radiationhardened registers.