Article Dans Une Revue Solid-State Electronics Année : 2003

Very low Schottky barrier to n-type silicon with PtEr-stack silicide

Résumé

We investigate Er silicide formed on n-type silicon. In order to protect the Er from oxidation during the formation of Er silicide in non-UHV conditions, a Pt layer is deposed successively on top of Er layer. Surprisingly, we observe that Pt remains essentially unaffected in the formation of Er silicide at temperatures lower than 700°C. We find that silicidation process is fully completed by rapid thermal annealing at 500°C. A simplified method of analysis considering the final Schottky barrier MOSFET application has been used to characterize the Schottky barrier of the PtEr-stack silicide system. A very low apparent Schottky barrier (smaller than 0.1 eV) on a n-type silicon substrate with a concentration of 1.4 × 10$^{16}$ cm$^{−3}$ in the active region has been obtained.

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hal-00146401 , version 1 (20-09-2024)

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Xing Tang, J. Katcki, Emmanuel Dubois, N. Reckinger, J. Ratajczak, et al.. Very low Schottky barrier to n-type silicon with PtEr-stack silicide. Solid-State Electronics, 2003, 47 (11), pp.2105-2111. ⟨10.1016/S0038-1101(03)00256-9⟩. ⟨hal-00146401⟩
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