Article Dans Une Revue IEEE Electron Device Letters Année : 2004

Schottky-barrier source/drain MOSFETs on ultra-thin silicon-on-insulator body with a tungsten metallic midgap gate

Résumé

This letter presents a simple low-temperature process to fabricate Schottky-barrier (SB) MOSFETs that integrates a midgap metallic gate (tungsten). The device architecture is based on a thin (10 nm) and lowly doped silicon-on-insulator film that provides a threshold voltage of -0.3 V independent on the depletion charge and therefore not sensitive to variations in film thickness and doping. A gate encapsulation technique using an SiO/sub 2/-like hydrogen silsesquioxane capping layer features 15-nm-wide spacers and ensures the compatibility with the PtSi self-aligned silicide process. Long-channel devices present an ideal subthreshold swing of 60 mV/dec, over six decades of I/sub on//I/sub off/ without any sign of sublinear upward bending of the I/sub DS/--V/sub DS/ curves at low drain voltage.

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Dates et versions

hal-00140981 , version 1 (20-09-2024)

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G. Larrieu, Emmanuel Dubois. Schottky-barrier source/drain MOSFETs on ultra-thin silicon-on-insulator body with a tungsten metallic midgap gate. IEEE Electron Device Letters, 2004, 25, pp.801-803. ⟨10.1109/LED.2004.838053⟩. ⟨hal-00140981⟩
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