Avalanche Behavior of Low-Voltage Power MOSFETs
Résumé
This letter addresses the behavior of low voltage power MOSFETs under avalanche, with a paralleling point of view. It is shown that during avalanche, up-to-date technology MOSFET transistors exhibit a resistance far in excess of their on-state resistance ( DS ). A novel test setup is proposed to measure “avalanche” resistance. A simple model of breakdown voltage is then proposed. It becomes possible to perform fast simulations using this model to study current balance between paralleled transistors under avalanche operation. It is shown that considering avalanche resistance reduces the influence of breakdown voltage mismatches and allows for better current sharing.
Fichier principal
IEEE-PWEL_2-3_2004_104_Buttay_AvalancheBehavior.pdf (200.03 Ko)
Télécharger le fichier
| Origine | Fichiers éditeurs autorisés sur une archive ouverte |
|---|
Loading...