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Article Dans Une Revue IEEE Transactions on Electron Devices Année : 2004

Design optimization of AlInAs-GaInAs HEMTs for low-noise applications

Résumé

In order to optimize the low-noise performance of 50-nm-gate AlInAs-GalnAs high-electron mobility transistors (HEMTs), by using an ensemble Monte Carlo simulation we study the influence of three important technological parameters on their noise level: the doping of the /spl delta/-doped layer, the width of the devices and the length of the recess. The noise behavior of the devices is firstly analyzed in terms of the physics-based P, R, and C parameters, and then characterized from a practical (circuit oriented) point of view through their four noise parameters: minimum noise figure, F/sub min/, noise resistance, R/sub n/, and complex input admittance, Y/sub opt/ (or reflection coefficient, /spl Gamma//sub opt/). We have observed an enhancement of the noise when the /spl delta/-doping or the device width are increased (a deterioration parallel to that of f/sub max/). Thus, the optimum noise operation is obtained for the lowest possible values of the /spl delta/-doping and device width. However, for small width the effect of the offset parasitic capacitances makes F/sub min/ increase, thus, imposing a limit for the reduction of the noise. Moreover, the increase of R/sub n/ for small W makes the noise tuning condition critical to reach the optimum low-noise operation. We have also confirmed that when shortening the recess length from 100 to 20 nm at each side of the gate F/sub min/ is reduced, with a slight deterioration of f/sub max/, while the static characteristics are not modified.
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Dates et versions

hal-00133870 , version 1 (28-02-2007)

Identifiants

Citer

Javier Mateos, Tomás González, Daniel Pardo, S. Bollaert, Thierry Parenty, et al.. Design optimization of AlInAs-GaInAs HEMTs for low-noise applications. IEEE Transactions on Electron Devices, 2004, 51 (8), pp.1228-1233. ⟨10.1109/TED.2004.832095⟩. ⟨hal-00133870⟩
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