Module selection is a basic architectural synthesis task that allows to optimise the cost of the dedicated circuits under real time constraint. Adding the power factor to the optimisation problem changes the working domain from two dimensions (Area/Time) to three dimensions (Area/Time/Power). However solving this problem by the best selection of the supply voltage and the operators set in a complex library remains unsolved. This paper presents an implementation of the module selection integrated in HLS GAUT tool and some results on a DWT algorithm.