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Conference Papers Year : 2005

A clock-less low-voltage AES crypto-processor


This paper presents a concrete evaluation of Quasi Delay Insensitive (QDI) Asynchronous logic in terms of current consumption within a wide range of supply voltages. The circuit designed and fabricated is a QDI AES (Advanced Encryption Standard) crypto-processor, compliant with the NIST standard: 128 bit data blocks and 128, 192 or 256 bit keys. This circuit exploits the fundamental properties of the Quasi Delay Insensitive Asynchronous logic, especially delay insensitivity, to enable relaxed operating conditions. The circuit, powered at 1.2 volt, ciphers a 128 bit data using a 128 bit key in 910 ns which corresponds to a ciphering rate of 141 Mbits per second. Due to the robustness of the clock-less Quasi Delay Insensitive logic, the circuit is functional within a wide voltage range, down to 0.4 Volt. With such a low supply voltage the chip consumes 200 µA sustaining a ciphering data rate of 6.4 Mbits/s. This work demonstrates that QDI asynchronous logic is particularly interesting in secure, low-voltage and low-power applications.
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Dates and versions

hal-00096996 , version 1 (20-09-2006)



Ghislain Fraidy Bouesse, Marc Renaudin, A. Witon, F. Germain. A clock-less low-voltage AES crypto-processor. Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European, 2005, Grenoble, France. pp.403- 406, ⟨10.1109/ESSCIR.2005.1541645⟩. ⟨hal-00096996⟩


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