Automatic Parametric Verification of Root Contention Protocol based on Abstract State Machines and First Order Timed Logic - Archive ouverte HAL
Communication Dans Un Congrès Année : 2004

Automatic Parametric Verification of Root Contention Protocol based on Abstract State Machines and First Order Timed Logic

Résumé

The paper presents a verification of the IEEE Root Contention Protocol as an illustration of a new and innovative approach for the verification of real-time distributed systems. Systems are modeled with basic Gurevich abstract state machines (ASMs), and requirements are expressed in a first order timed logic (FOTL). FOTL is undecidable, however the protocol we study is in a decidable class of practical interest. Advantages of this framework are twofold: on the one hand, a great expressive power which permits in particular an easy treatment of parameters, on the other hand the modeling task is simplified by an adequat choice of tools.
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Dates et versions

hal-00094616 , version 1 (14-09-2006)

Identifiants

  • HAL Id : hal-00094616 , version 1

Citer

Danièle Beauquier, Tristan Crolard, Evguenia Prokofieva. Automatic Parametric Verification of Root Contention Protocol based on Abstract State Machines and First Order Timed Logic. TACAS, 2004, France. pp.372-387. ⟨hal-00094616⟩

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