This paper proposes a method for energy consumption estimation and optimisation on hardware-software embedded systems-on-chip. The aim of our work is to provide a simulation framework enabling power estimations of high level descriptions (behavioural C models) of systems that include all the hardware components also the new ones. Such analysis are needed to select the best hardware architecture and software organization for a particular application in terms of power consumption and to apply low power techniques at system level.The starting point is the architectural description of the system used for simulation. It employs very abstract C-based models of the hardware components. We focus on the cycle-accurate level to improve the estimation accuracy. Behavioural models are extended with energy models that take into account the operations executed per transition into the state machines of the components.The method has been tested in a MPEG4 decoder implementation. The error of the energy estimations was estimated lower than 6% from physical measurements. Low power techniques were applied and analyzed like another memory hierarchy, clock gating, voltage/frequency scaling, and some others. It has permitted to reduce the consumption cost of the system on 93%.