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Article Dans Une Revue ACM Transactions on Embedded Computing Systems (TECS) Année : 2006

A Formal Method for Hardware IP Design and Integration under I/O and Timing Constraints

Philippe Coussy
Pierre Bomel
Adel Baganne
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Eric Martin
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Résumé

IP integration -that is one of the most important SoC design steps- requires taking into account communication and timing constraints. In that context design and reuse can be improved using IP cores described at a high abstraction level. In this paper we present an IP design approach that relies on three main phases: (1) constraint modeling, (2) IP constraint analysis steps for feasibility checking and (3) synthesis. We propose a set of techniques dedicated to the digital signal processing domain that lead to an optimized IP core integration. Based on a generic architecture of component, the method we propose provides automatic generation of IP cores designed under integration constraints. We show the effectiveness of our approach with a DCT core design case study.
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Dates et versions

hal-00077729 , version 1 (01-06-2006)

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Citer

Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin. A Formal Method for Hardware IP Design and Integration under I/O and Timing Constraints. ACM Transactions on Embedded Computing Systems (TECS), 2006, vol 5, No. 1, pp.29-53. ⟨10.1145/1132357.1132359⟩. ⟨hal-00077729⟩
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