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Communication Dans Un Congrès Année : 2004

A Memory Aware behavioral Synthesis Tool for Real-Time VLSI Circuits

Nathalie Julien
Eric Martin
  • Fonction : Auteur
  • PersonId : 831063
Eric Senn

Résumé

We introduce a new approach to take into account the memory architecture and the memory mapping in the Behavioral Synthesis of Real-Time VLSI circuits. We formalize the memory mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We use a memory mapping .le to include those memory constraints in our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time. Several experiments are performed to demonstrate the efficiency of our method, and to compare GAUT with an industrial behavioral synthesis tool. We finally show how to explore, with the help of GAUT, a wide range of solutions, and to reach a good tradeoff. between time, power-consumption, and area.
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Dates et versions

hal-00077370 , version 1 (31-05-2006)

Identifiants

  • HAL Id : hal-00077370 , version 1

Citer

Gwenolé Corre, Nathalie Julien, Eric Martin, Eric Senn. A Memory Aware behavioral Synthesis Tool for Real-Time VLSI Circuits. ACM Great Lake Symposium on VLSI, 2004, Boston, France. pp.82-85. ⟨hal-00077370⟩
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