An Approach Combining Simulation and Verification for SysML using SystemC and Uppaal - Université de Technologie de Belfort-Montbeliard Access content directly
Conference Papers Year : 2014

An Approach Combining Simulation and Verification for SysML using SystemC and Uppaal

Abstract

Ensuring the correction of heterogeneous and complex systems is an essential stage in the process of engineering systems. In this paper we propose a methodology to verify and validate complex systems specified with SysML language using a combination of the two techniques of simulation and verification. We translate SysML specifications into SystemC models to validate the designed systems by simulation, then we propose to verify the derived SystemC models by using the Uppaal model checker. A case study is presented to demonstrate the effectiveness of our approach.
Fichier principal
Vignette du fichier
ahmt14:onp-author.pdf (1023.96 Ko) Télécharger le fichier
Origin Files produced by the author(s)

Dates and versions

hal-01234020 , version 1 (26-11-2015)

Identifiers

  • HAL Id : hal-01234020 , version 1

Cite

Abbas Abdulhameed, Ahmed Hammad, Hassan Mountassir, Bruno Tatibouët. An Approach Combining Simulation and Verification for SysML using SystemC and Uppaal. CAL 2014, 8ème conférence francophone sur les architectures logicielles, 2014, Paris, France. 9 p. ⟨hal-01234020⟩
174 View
279 Download

Share

Gmail Mastodon Facebook X LinkedIn More