Data and Thread Placement in NUMA Architectures: A Statistical Learning Approach - Archive ouverte HAL Access content directly
Conference Papers Year :

Data and Thread Placement in NUMA Architectures: A Statistical Learning Approach

(1) , (2) , (2) , (3, 4, 5)
1
2
3
4
5

Abstract

Nowadays, NUMA architectures are common in compute-intensive systems. Achieving high performance for multi-threaded application requires both a careful placement of threads on computing units and a thorough allocation of data in memory. Finding such a placement is a hard problem to solve, because performance depends on complex interactions in several layers of the memory hierarchy. In this paper we propose a black-box approach to decide if an application execution time can be impacted by the placement of its threads and data, and in such a case, to choose the best placement strategy to adopt. We show that it is possible to reach near-optimal placement policy selection. Furthermore, solutions work across several recent processor architectures and decisions can be taken with a single run of low overhead profiling.
Fichier principal
Vignette du fichier
paper.pdf (790.77 Ko) Télécharger le fichier
Origin : Files produced by the author(s)
Loading...

Dates and versions

hal-02135545 , version 1 (21-05-2019)
hal-02135545 , version 2 (10-06-2019)
hal-02135545 , version 3 (30-07-2019)

Identifiers

Cite

Nicolas Denoyelle, Brice Goglin, Emmanuel Jeannot, Thomas Ropars. Data and Thread Placement in NUMA Architectures: A Statistical Learning Approach. ICPP 2019 - 48th International Conference on Parallel Processing, Aug 2019, Kyoto, Japan. pp.1-10, ⟨10.1145/3337821.3337893⟩. ⟨hal-02135545v3⟩
248 View
535 Download

Altmetric

Share

Gmail Facebook Twitter LinkedIn More