3D IC Interconnect Parasitic Capacitance Extraction with a Reformulated PGD Algorithm - Laboratoire d'Electronique et Electromagnétisme Accéder directement au contenu
Communication Dans Un Congrès Année : 2016

3D IC Interconnect Parasitic Capacitance Extraction with a Reformulated PGD Algorithm

Résumé

Proper generalized decomposition (PGD) is a new model order reduction (MOR) method based on the use of separated representations. In this work, PGD is applied on 3D capacitance extraction of interconnects in IC to reduce its computational complexity. To make the PGD solver feasible, the complex geometries are simplified by a characteristic function technique. 3D singular value decomposition (SVD) of the characteristic functions is avoided by a reformulation of the PGD algorithm. A numerical example is given to verify the method.
Fichier non déposé

Dates et versions

hal-01513819 , version 1 (25-04-2017)

Identifiants

Citer

Yalan Li, Shuai Yan, Xiaoyu Xu, Pengfei Lyu, Zhuoxiang Ren. 3D IC Interconnect Parasitic Capacitance Extraction with a Reformulated PGD Algorithm. Conference CEFC 2016, Nov 2016, Miami (Floride), United States. ⟨10.1109/CEFC.2016.7816140⟩. ⟨hal-01513819⟩
56 Consultations
0 Téléchargements

Altmetric

Partager

Gmail Facebook X LinkedIn More