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Article Dans Une Revue IEEE Access Année : 2022

Theory and Original Design of Resistive-Inductive Network High-Pass Negative Group Delay Integrated Circuit in 130-nm CMOS Technology

Résumé

This paper develops an original design method of high-pass (HP) negative group delay (NGD) integrated circuit (IC). The considered HP-NGD IC is based on a passive topology which is essentially composed of resistor-inductor (RL) network. The paper presents the first time that an unfamiliar HPtopology is designed in miniaturized circuit implemented in 130-nm CMOS technology. The theory of unfamiliar HP-NGD topology based on the voltage transfer function (VTF) analysis is elaborated. The design equations with synthesis formulas of the resistor and inductor are established. The HP-NGD IC CMOS design methodology is introduced. The feasibility of the miniature NGD IC implementation is approved by design rule check (DRC) and layout versus schematic (LVS) approaches. The HP-NGD passive IC is designed in 130-nm CMOS technology. The HP-NGD topology is constituted by RL-network based on CMOS high Ohmic unsalicided N + poly resistor and symmetrical high current spiral inductor. Then, the schematic and layout simulations are presented. The validity of the 130-nm CMOS HP-NGD design is verified by the investigation of 225 µm × 215 µm chip two different miniature circuit proofs-of-concept (POC). The HP-NGD behavior is validated by comparison between the calculated, and schematic and post-layout simulations of the HP-NGD POCs carried out by a commercial tool. As expected, the group delay and VTF magnitude diagrams are in very good correlation. HP-NGD optimal value, NGD cutoff frequency and attenuation, of about (−31 ps, 141 MHz, −3 dB) and (−47 ps, 204 MHz, −5 dB) are obtained from the miniature POCs. INDEX TERMS 130-nm CMOS technology, design method, negative group delay (NGD), high-pass (HP) NGD function, HP-NGD theory, integrated circuit (IC) design, synthesis equation, RL-network passive topology, miniature circuit.
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Dates et versions

hal-03969177 , version 1 (02-02-2023)

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Paternité

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Mathieu Guerin, Wenceslas Rahajandraibe, Glauco Fontgalland, Hugerles S Silva, George Chan, et al.. Theory and Original Design of Resistive-Inductive Network High-Pass Negative Group Delay Integrated Circuit in 130-nm CMOS Technology. IEEE Access, 2022, 10, pp.27147-27161. ⟨10.1109/ACCESS.2022.3157381⟩. ⟨hal-03969177⟩
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