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Industrial characterization of scatterometry for advanced APC of 65 nm CMOS logic gate patterning

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Abstract

CMOS 65nm technology node requires the introduction of advanced materials for critical patterning operations. The study is focused on the multilayer Anti Reflective Coating (ARC) stack, used in photolithography, for the gate patterning such as Advanced Patterning Film (APF). The interest on this new and complex ARC stack lies in the benefit to guarantee low CD dispersion thanks to a better reflectivity control and resist budget which leads to a larger lithographic process window. However, it implies numerous metrology challenges. The paper deals with the challenges of monitoring the gate Critical Dimension (CD) on this stack. The validation of the scatterometry model versus stack thicknesses and indexes variations, through experiments, is also described. The final result is the complete characterization of the materials for thickness and scatterometry CD control, for photo feedback and for etch feed-forward deployment in an industrial mode. The analysis shows that scatterometry measurements on a standard 65 nm gate process ensure a better effectiveness than the CD Scanning Electron Microscopy (SEM) ones when injected in the Advanced Process Control (APC) system from photo to etch.
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Dates and versions

hal-00462558 , version 1 (28-09-2022)

Licence

Attribution - CC BY 4.0

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Karen Dabertrand, Mathieu Touchet, Stéphanie Kremer, Catherine Chaton, Maxime Gatefait, et al.. Industrial characterization of scatterometry for advanced APC of 65 nm CMOS logic gate patterning. SPIE Advanced Lithography, 2008, San Jose, United States. ⟨10.1117/12.771614⟩. ⟨hal-00462558⟩
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